The Spark i0 delivers a flexible, high-performance platform for network-centric FPGA applications. This board, built around the Lattice ECP5 family, combines cost-effective design, low power operation, and advanced connectivity. Ideal for developers building custom Ethernet systems, hardware network processors, and edge computing solutions.
Key Features
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Lattice ECP5 FPGA Core
Available in multiple density options (up to 45K LUTs), offering an optimal balance between logic resources and power efficiency. The ECP5 architecture enables efficient implementation of Ethernet MACs, custom packet engines, and timing-sensitive logic. -
8× Gigabit Ethernet Interfaces
Eight fully independent Gigabit Ethernet ports with RGMII connectivity to VSC8541XMV-02 PHYs. Each port is directly accessible to the FPGA fabric for maximum flexibility in packet processing, switching, or protocol acceleration. -
Integrated Memory Subsystem
Includes onboard 128 kB asynchronous SRAM for data management, plus 2 MB SPI Flash for configuration storage and embedded firmware. -
Precision Clocking and Synchronization
125 MHz low-jitter reference clock with programmable PLLs to support multiple clock domains and synchronous timestamping—ideal for Time-Sensitive Networking (TSN) or PTP/IEEE 1588 applications. -
Expansion and Debug Interfaces
Two PMOD connectors and a UART-over-USB interface provide easy expansion and system monitoring. Optional FMC or high-speed headers allow integration with external PHYs, ADCs, or custom I/O modules. -
Comprehensive Toolchain Support
Fully supported by Lattice Diamond design suites, with example projects for Ethernet packet forwarding, MAC loopback, and FPGA-based network monitoring. -
Optimized Power and Thermal Design
Efficient DC-DC regulation supports stable multi-rail operation from a single 5V input. Passive cooling ensures reliable performance for extended workloads.
Applications
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FPGA-based Ethernet switches and media converters
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Network protocol analyzers and hardware firewalls
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Edge and industrial IoT gateways
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Time-sensitive networking (TSN) and deterministic Ethernet control
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Research and education in FPGA-based networking architectures
Technical Specifications
| Feature | Description |
|---|---|
| FPGA | Lattice ECP5 (LFE5U or LFE5UM family, up to 85K LUTs) |
| Ethernet Ports | 8 × 1Gbps RGMII |
| Memory | 512 MB–1 GB DDR3, 64 MB QSPI Flash |
| Clocking | 125 MHz reference, programmable PLLs |
| Expansion | 2× PMOD, UART, optional FMC |
| Power Input | 5V DC (onboard regulation) |
| Software Tools | Lattice Diamond, example VHDL and Verilog reference projects |
| Board Size | 160 mm x 85 mm |